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ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply. * samsung electronics reserves the right to change products or specification without notice. 66 tsop-ii ddr sdram unbuffered module 184pin unbuffered module based on 512mb b-die with 64/72-bit non ecc/ecc www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 table of contents 1.0 ordering information...... ................ ................. ................ ................ ................. ............... ............ 4 2.0 operating frequencies..... ................. ................ ................ ................. ................ ............... .......... 4 3.0 feature............. ................ ................ .............. .............. .............. ............... .............. ........... ........... 4 4.0 pin configuration (front side/back side) ..... ................ ................ ................. .............. ............. 5 5.0 pin description .......... ................. ................ ................ ................. ................ ................ ................ 5 6.0 functional block diagram ........... ................ ................. .............. .............. .............. ............. ....... 6 6.1 256mb, 32m x 64 non ecc m odule (m368l3324bt(u)).... ................ ................ ............. ............. ............. .......... 6 6.2 512mb, 64m x 64 non ecc m odule (m368l6523bt(u)) ...... ................. ................ ............. ............ ........... ......... 7 6.3 512mb, 64m x 72 ecc module (m381l6523b(u)) .......... ................ ................ ............. ............. ............ .............. 8 6.4 1gb, 128m x 64 non ecc m odule (m368l2923bt(u)) ...... ................ ................ ............. ............. ............ ........... 9 6.5 1gb, 128m x 72 e cc module (m381l2923bt(u)) ... ................. ................ ................ ................ ............ ........... 10 7.0 absolute maximum ratings........... ................. ................ .............. .............. .............. ............. ... 11 8.0 dc operating conditions.... ................ ................ ................. ................ ................. .............. ...... 11 9.0 ddr sdram idd spec table . ................ ................. ................ ................. ................ ................ .. 12 9.1 m368l3324bt(u) [ (32m x 16) * 4, 256mb non ecc module ] ............................................................................... 12 9.2 m368l6523bt(u) [ (64m x 8) * 8, 512mb non ecc module ] ................................................................................. 12 9.3 m381l6523bt(u) [ (64m x 8) * 9, 512mb ecc module ] .......................................................................................... 13 9.4 m368l2923bt(u) [ (64m x 8) * 16, 1gb non ecc module ] .................................................................................... 13 9.5 m381l2923bt(u) [ (64m x 8) * 18, 1gb ecc module ] ............................................................................................ 14 10.0 ac operating conditions.... ................ ................. ................ ................. ................ ............. ..... 15 11.0 input/output capacitance .......... ................ ................. .............. .............. .............. ............. ..... 15 12.0 ac timming parameters & specificat ions ................ ................ ................. ................ ........... 16 13.0 system characteristics for ddr sdram ........... .............. .............. .............. .............. ........... 17 14.0 component notes......... ................ ................. ................ ................ ................. ................ ......... 18 15.0 system notes ........... ................. ................ ................ ................. ................ ................. ............. 19 16.0 command truth table.................. .............. .............. .............. ............... .............. .............. ...... 20 17.0 physical dimensions...... ................. ................ ................ ................. ................ ............... ........ 21 17.1 32m x 64 (m368l3324bt(u)) ................. ................. .............. .............. .............. .............. ........... 21 17.2 64mx64 (m368l6523bt(u)) ................. ................ ................. .............. .............. .............. ........... 22 17.3 64mx72 (m381l6523bt(u)) ................. ................ ................. .............. .............. .............. ........... 23 17.4 128mx64 (m368l2923bt(u)) ................. ................. .............. .............. .............. .............. ........... 24 17.5 128mx72 (m381l2923bt(u)) ................. ................. .............. .............. .............. .............. ........... 25 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 revision history revision month year history 0.0 february 2003 - first version for internal review 1.0 august 2003 - revision 1.0 spec release. 1.1 june 2005 - deleted ?b0, aa, a2? speed and changed master format. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 cc(ddr400@cl=3) b3(ddr333@cl=2.5) speed @cl2 - 133mhz speed @cl2.5 166mhz 166mhz speed @cl3 200mhz - cl-trcd-trp 3-3-3 2.5-3-3 184pin unbuffered dimm based on 512mb b-die (x8, x16) ? vdd : 2.5v 0.2v, vddq : 2.5v 0.2v for ddr333 ? vdd : 2.6v 0.1v, vddq : 2.6v 0.1v for ddr400 ? double-data-rate architecture; tw o data transfers per clock cycle ? bidirectional data strobe [dq] (x4,x8) & [l(u)dqs] (x16) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency : ddr333(2.5 clock), ddr400(3 clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us re fresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1,250 (mil) & single (256, 512mb), double (1gb) sided ? sstl_2 interface ? 66pin tsop ii (leaded & pb-free(rohs compliant)) package 1.0 ordering information 2.0 operating frequencies note : leaded and lead-free(pb-free) can be discriminated by pkg p/n (t : 66 tsop with leaded, u : 66 tsop with lead-free) part number density organization component composition height m368l3324bt(u)m-c(l)cc/b3 256mb 32m x 64 32mx16 (k4h511638b) * 4ea 1,250mil m368l6523bt(u)m-c(l)cc 512mb 64m x 64 64mx8 (k4h510838b) * 8ea 1,250mil m368l6523bt(u)n-c(l)b3 m381l6523bt(u)m-c(l)cc/b3 512mb 64m x 72 64mx8 (k4h510838b) * 9ea 1,250mil m368l2923bt(u)m-c(l)cc 1gb 128m x 64 64mx8 (k4h510838b) * 16ea 1,250mil m368l2923bt(u)n-c(l)b3 m381l2923bt(u)m-c(l)cc/b3 1gb 128m x 72 64mx8 (k4h510838b) * 18ea 1,250mil 3.0 feature www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 note : 1. * : these pins are not used in this module. 2. pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are us ed on x72 module ( m381~ ), and are not used on x64 module. 3. pins 111, 158 are nc for 1row modul es & used for 2row modules[ m368(81)l2923b ]. 4. pins 137, 138 are nc for x16 1row module (m368l3324b). pin front pin front pin front pin back pin back pin back 1 vref 32 a5 62 vddq 93 vss 124 vss 154 ras 2 dq0 33 dq24 63 we 94 dq4 125 a6 155 dq45 3 vss 34 vss 64 dq41 95 dq5 126 dq28 156 vddq 4 dq1 35 dq25 65 cas 96 vddq 127 dq29 157 cs0 5 dqs0 36 dqs3 66 vss 97 dm0 128 vddq 158 cs1 6 dq2 37 a4 67 dqs5 98 dq6 129 dm3 159 dm5 7 vdd 38 vdd 68 dq42 99 dq7 130 a3 160 vss 8 dq3 39 dq26 69 dq43 100 vss 131 dq30 161 dq46 9 nc 40 dq27 70 vdd 101 nc 132 vss 162 dq47 10 nc 41 a2 71 *cs2 102 nc 133 dq31 163 *cs3 11 vss 42 vss 72 dq48 103 nc 134 cb4 164 vddq 12 dq8 43 a1 73 dq49 104 vddq 135 cb5 165 dq52 13 dq9 44 cb0 74 vss 105 dq12 136 vddq 166 dq53 14 dqs1 45 cb1 75 *ck2 106 dq13 137 ck0 167 *a13 15 vddq 46 vdd 76 *ck2 107 dm1 138 ck0 168 vdd 16 ck1 47 dqs8 77 vddq 108 vdd 139 vss 169 dm6 17 ck1 48 a0 78 dqs6 109 dq14 140 dm8 170 dq54 18 vss 49 cb2 79 dq50 110 dq15 141 a10 171 dq55 19 dq10 50 vss 80 dq51 111 cke1 142 cb6 172 vddq 20 dq11 51 cb3 81 vss 112 vddq 143 vddq 173 nc 21 cke0 52 ba1 82 vddid 113 *ba2 144 cb7 174 dq60 22 vddq key 83 dq56 114 dq20 key 175 dq61 23 dq16 53 dq32 84 dq57 115 a12 145 vss 176 vss 24 dq17 54 vddq 85 vdd 116 vss 146 dq36 177 dm7 25 dqs2 55 dq33 86 dqs7 117 dq21 147 dq37 178 dq62 26 vss 56 dqs4 87 dq58 118 a11 148 vdd 179 dq63 27 a9 57 dq34 88 dq59 119 dm2 149 dm4 180 vddq 28 dq18 58 vss 89 vss 120 vdd 150 dq38 181 sa0 29 a7 59 ba0 90 nc 121 dq22 151 dq39 182 sa1 30 vddq 60 dq35 91 sda 122 a8 152 vss 183 sa2 31 dq19 61 dq40 92 scl 123 dq23 153 dq44 184 vddspd note : vddid defines relationship of vdd and vddq , and the default status of it is open (vdd=vddq) pin name function pin name function a0 ~ a12 address input (multiplexed) dm0 ~7,8(for ecc) data - in mask ba0 ~ ba1a bank select address vdd power supply (2.5v for ddr333, 2.6v for ddr400) dq0 ~ dq63 data input/output vddq power supply for dqs (2.5v for ddr333, 2.6v for ddr400) dqs0 ~ dqs8 data strobe input/output vss ground ck0,ck0 ~ ck2, ck2 clock input vref power supply for reference cke0, cke1(for double banks) clock enable input vddspd serial eeprom power/supply ( 2.3v to 3.6v ) cs0 , cs1 (for double banks) chip select input sda serial data i/o ras row address strobe scl serial clock cas column address strobe sa0 ~ 2 address in eeprom we write enable vddid vdd, vddq level detection cb0 ~ cb7(for x72 module) check bi t(data-in/data-out) nc no connection 5.0 pin description 4.0 pin configuration (f ront side/back side) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (populated as 1 bank of x16 ddr sdram module) 6.1 256mb, 32m x 64 non ecc module (m368l3324bt(u)) 6.0 functional block diagram dq13 dq14 dq12 dq15 ldm i/o 0 i/o 1 i/o 2 i/o 3 d0 dq9 dq10 dq8 i/o 4 i/o 5 i/o 6 udm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dq3 dq4 dq7 dq5 dq2 dq1 dq6 dq0 dq29 dq26 dq25 dq30 d1 dq28 dq27 dq24 dq31 dq20 dq23 dq16 dq19 dq17 dq22 dq21 dq18 d3 dm1 cs cs cs ldqs dqs1 dm0 dqs0 udqs a0 - a12 a0-a12: ddr sdrams d0 - d3 ba0 - ba1 ba0-ba1: ddr sdrams d0 - d3 ras ras : ddr sdrams d0 - d3 cas cas : ddr sdrams d0 - d3 cke0 cke: ddr sdrams d0 - d3 we we : ddr sdrams d0 - d3 clock wiring ck0/ck0 clock input ddr sdrams ck1/ck1 nc 2 ddr sdrams 2 ddr sdrams ck2/ck2 cs0 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d3 d0 - d3 v dd /v ddq d0 - d3 d0 - d3 vref v ddspd spd notes: 1. dq-to-i/o wiring is shown as recomended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 7.5 ohms + 5% dq11 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dq41 dq42 dq45 dq43 i/o 0 i/o 1 i/o 2 i/o 3 dq44 dq46 dq40 i/o 4 i/o 5 i/o 6 dq47 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dq35 dq36 dq39 dq33 dq38 dq37 dq34 dq32 dq57 dq62 dq56 dq58 dq61 dq63 dq60 dq59 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq48 dq51 dq52 dq50 dq49 dq55 dq53 dq54 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 d2 cs ldm dm5 ldqs dqs5 udm dm0 dqs0 udqs ldm dm3 ldqs dqs3 udm dm0 dqs0 udqs ldm dm3 ldqs dqs3 udm dm0 dqs0 udqs www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (populated as 1 bank of x8 ddr sdram module) 6.2 512mb, 64m x 64 non ecc module (m368l6523bt(u)) cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 6 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 3 i/o 1 i/o 7 i/o 5 i/o 1 i/o 0 i/o 6 i/o 4 i/o 3 i/o 2 i/o 6 i/o 5 i/o 3 i/o 0 i/o 7 i/o 4 i/o 2 i/o 1 i/o 7 i/o 4 i/o 2 i/o 1 i/o 6 i/o 5 i/o 3 i/o 0 i/o 7 i/o 4 i/o 1 i/o 3 i/o 6 i/o 5 i/o 0 i/o 2 i/o 6 i/o 4 i/o 3 i/o 1 i/o 7 i/o 5 i/o 2 i/o 0 i/o 7 i/o 5 i/o 1 i/o 0 i/o 6 i/o 4 i/o 3 i/o 2 i/o 5 i/o 4 i/o 1 i/o 0 i/o 7 i/o 6 i/o 3 i/o 2 a0 - a12 a0-a12 : ddr sdrams d0 - d7 ras ras : ddr sdrams d0 - d7 cas cas : ddr sdrams d0 - d7 we we : ddr sdrams d0 - d7 cke0 cke : ddr sdrams d0 - d7 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d7 v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddspd spd d0 - d7 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 2 ddr sdrams 3 ddr sdrams 3 ddr sdrams card edge d3/d0/d5 cap/cap/cap cap/d1/d6 cap/cap/cap d4/d2/c7 cap/cap/cap r=120 ? ck0/1/2 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% ck0/1/2 cap www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (populated as 1 bank of x8 ddr sdram module) 6.3 512mb, 64m x 72 e cc module (m381l6523bt(u)) a0 - a12 a0-a12 : ddr sdrams d0 - d8 ras ras : ddr sdrams d0 - d8 cas cas : ddr sdrams d0 - d8 we we : ddr sdrams d0 - d8 cke0 cke : ddr sdrams d0 - d8 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d8 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd spd d0 - d8 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 3 ddr sdrams 3 ddr sdrams 3 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 6 i/o 4 i/o 2 i/o 0 i/o 7 i/o 5 i/o 3 i/o 1 i/o 7 i/o 5 i/o 1 i/o 0 i/o 6 i/o 4 i/o 3 i/o 2 i/o 6 i/o 5 i/o 3 i/o 0 i/o 7 i/o 4 i/o 2 i/o 1 i/o 7 i/o 4 i/o 3 i/o 1 i/o 6 i/o 5 i/o 2 i/o 0 i/o 7 i/o 4 i/o 3 i/o 0 i/o 6 i/o 5 i/o 2 i/o 1 i/o 6 i/o 4 i/o 3 i/o 2 i/o 7 i/o 5 i/o 1 i/o 0 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 5 i/o 4 i/o 1 i/o 0 i/o 7 i/o 6 i/o 3 i/o 2 dqs8 dm8 dm/ cs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 i/o 5 i/o 4 i/o 3 i/o 1 i/o 7 i/o 6 i/o 2 i/o 0 card edge d3/d0/d6 cap/cap/cap d4/d1/d7 cap/cap/cap d5/d2/d8 cap/cap/cap r=120 ? ck0/1/2 ck0/1/2 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (populated as 2 bank of x8 ddr sdram module) 6.4 1gb, 128m x 64 non ec c module (m368l2923bt(u)) cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 5 i/o 6 i/o 1 i/o 0 i/o 7 i/o 4 i/o 3 i/o 2 i/o 5 i/o 4 i/o 1 i/o 0 i/o 7 i/o 6 i/o 3 i/o 2 i/o 5 i/o 6 i/o 1 i/o 0 i/o 7 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 2 i/o 5 i/o 4 i/o 3 i/o 0 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 2 i/o 5 i/o 4 i/o 3 i/o 0 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d8 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d12 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 cs 1 i/o 2 i/o 1 i/o 6 i/o 7 i/o 0 i/o 3 i/o 4 i/o 5 i/o 2 i/o 3 i/o 6 i/o 7 i/o 0 i/o 1 i/o 4 i/o 5 i/o 2 i/o 1 i/o 6 i/o 7 i/o 0 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 5 i/o 2 i/o 3 i/o 4 i/o 7 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 5 i/o 2 i/o 3 i/o 4 i/o 7 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 a0 - a12 a0-a12: ddr sdrams d0 - d15 ras ras : ddr sdrams d0 - d15 cas cas : ddr sdrams d0 - d15 we we : ddr sdrams d0 - d15 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d15 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 vref v ddspd spd d0 - d15 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 4 ddr sdrams 6 ddr sdrams 6 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp card edge d3/d0/d5 d11/d8/d13 cap/d1/d6 cap/d9/d14 d4/d2/d7 d12/d10/d15 r=120 ? ck0/1/2 * * cke 0/1 cke : ddr sdrams d0 - d15 ck0/1/2 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 3 ohms + 5% www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (populated as 2 bank of x8 ddr sdram module) 6.5 1gb, 128m x 72 e cc module (m381l2923bt(u)) cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 cs 1 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 a0 - a12 a0-a12 : ddr sdrams d0 - d17 ras ras : ddr sdrams d0 - d17 cas cas : ddr sdrams d0 - d17 we we : ddr sdrams d0 - d17 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d17 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 6 ddr sdrams 6 ddr sdrams 6 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp card edge d3/d0/d5 d12/d9/d14 d8/d1/d6 d17/d10/d15 d4/d2/d7 d13/d11/d16 r=120 ? ck0/1/2 cke0/1 cke : ddr sdrams d0 - d17 dqs8 dm8 dm/ cs dqs d8 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d17 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors:3 ohms + 5% www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could af fect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd & v ddq supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) note : 1. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on v ref may not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination re sistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is s pecified for the same temperature and voltage, over the entire t emperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of t he maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v for ddr333) v dd 2.3 2.7 v supply voltage(for device with a nominal v dd of 2.6v for ddr400) v dd 2.5 2.7 v i/o supply voltage(for device with a nominal v dd of 2.5v for ddr333) v ddq 2.3 2.7 v i/o supply voltage(for device with a nominal v dd of 2.6v for ddr400) v ddq 2.5 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 8.0 dc operating conditions 7.0 absolute maximum ratings www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc(ddr400@cl=3) b3(ddr333@cl=2.5) unit notes idd0 660 500 ma idd1 760 620 ma idd2p 20 20 ma idd2f 120 120 ma idd2q 100 100 ma idd3p 220 120 ma idd3n 400 200 ma idd4r 920 780 ma idd4w 1,120 860 ma idd5 1,060 1,000 ma idd6 normal 20 20 ma low power 12 12 ma optional idd7a 1,800 1,620 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc(ddr400@cl=3) b3(ddr333@cl=2.5) unit notes idd0 1,320 1,000 ma idd1 1,480 1,200 ma idd2p 40 40 ma idd2f 240 240 ma idd2q 200 200 ma idd3p 440 240 ma idd3n 760 400 ma idd4r 1,600 1,320 ma idd4w 1,920 1,520 ma idd5 2,120 2,000 ma idd6 normal 40 40 ma low power 24 24 ma optional idd7a 3,440 3,200 ma 9.1 m368l3324bt(u) [ (32m x 16 ) * 4, 256mb non ecc module ] 9.2 m368l6523bt(u) [ (64m x 8) * 8, 512mb non ecc module ] 9.0 ddr sdram idd spec table www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc(ddr400@cl=3) b0(ddr333@cl=2.5) unit notes idd0 1,485 1,130 ma idd1 1,665 1,350 ma idd2p 45 45 ma idd2f 270 270 ma idd2q 225 230 ma idd3p 500 270 ma idd3n 855 450 ma idd4r 1,800 1,490 ma idd4w 2,160 1,710 ma idd5 2,385 2,250 ma idd6 normal 45 45 ma low power 27 27 ma optional idd7a 3,870 3,600 ma (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol cc(ddr400@cl=3) b0(ddr333@cl=2.5) unit notes idd0 2,080 1,400 ma idd1 2,240 1,600 ma idd2p 80 80 ma idd2f 480 480 ma idd2q 400 400 ma idd3p 880 480 ma idd3n 1,520 800 ma idd4r 2,360 1,720 ma idd4w 2,680 1,920 ma idd5 2,880 2,400 ma idd6 normal 80 80 ma low power 48 48 ma optional idd7a 4,200 3,600 ma 9.4 m368l2923bt(u) [ (64m x 8) * 16, 1gb non ecc module ] 9.3 m381l6523bt(u) [ (64m x 8) * 9, 512mb ecc module ] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd a nd can be differently measured according to dq loading cap. symbol cc (ddr400@cl=3) b3 (ddr333@cl=2.5) unit notes idd0 2,340 1,580 ma idd1 2,520 1,800 ma idd2p 90 90 ma idd2f 540 540 ma idd2q 450 450 ma idd3p 990 540 ma idd3n 1,710 900 ma idd4r 2,655 1,940 ma idd4w 3,015 2,160 ma idd5 3,240 2,700 ma idd6 normal 90 90 ma low power 54 54 ma optional idd7a 4,725 4,050 ma 9.5 m381l2923bt(u) [ (64m x 8) * 18, 1gb ecc module ] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq (vdd=2.5v, vddq=2.5v, ta= 25 c, f=1mhz) parameter symbol m368l3324bt(u) m368l6523bt(u) m381l6523bt(u) unit min max min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin1414549575160pf input capacitance(cke0) cin2 34 38 42 50 44 53 pf input capacitance( cs 0) cin3 34 38 42 50 44 53 pf input capacitance( clk0, clk1,clk2) cin4 25 30 25 30 25 30 pf input capacitance(dm0~dm7, dm8(for ecc)) cin5676767pf data & dqs input/output capacitance(dq0~dq63)cout1676767pf data input/output capacitance (cb0~cb7) cout2----67pf parameter symbol m368l2923bt(u) m381l2923bt(u) unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin165816987pf input capacitance(cke0,cke1) cin2 42 50 44 53 pf input capacitance( cs 0, cs 1) cin3 42 50 44 53 pf input capacitance( clk0, clk1,clk2) cin4 28 34 28 34 pf input capacitance(dm 0~dm7, dm8(for ecc)) cin5 10 12 10 12 pf data & dqs input/output capacitance(dq0~dq63) cout1 10 12 10 12 pf data input/output capacitance (cb0~cb7) cout2 - - 10 12 pf note : 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same. 3. these parameters should be tested at the pim on actual co mponents and may be checked at either the pin or the pad in simulation. the ac and dc input specificatims are refati on to a vref envelope that has been bandwidth limited 20mhz. parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dq s and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vdd q-0.2 0.5*vddq+0.2 v 2 11.0 input/output capacitance 10.0 ac operating conditions www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 parameter symbol cc (ddr400@cl=3.0) b3 (ddr333@cl=2.5) unit note min max min max row cycle time trc 55 60 ns refresh row cycle time trfc 70 72 ns row active time tras 40 70k 42 70k ns ras to cas delay trcd 15 18 ns row precharge time trp 15 18 ns row active to row active delay trrd 10 12 ns write recovery time twr 15 15 ns last data in to read command twtr 2 1 tck clock cycle time cl=2.0 tck --7.512ns cl=2.5 612612ns cl=3.0 5 10 - - clock high level width tch 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.55 +0.55 -0.6 +0.6 ns output data access time from ck/ck tac -0.65 +0.65 -0.7 +0.7 ns data strobe edge to ouput data edge tdqsq - 0.4 - 0.45 ns 22 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.72 1.28 0.75 1.25 tck dqs-in setup time twpres 0 0 ns 13 dqs-in hold time twpre 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 tck address and control input setup time(fast) tis 0.6 0.75 ns 15, 17~19 address and control input hold time(fast) tih 0.6 0.75 ns 15, 17~19 address and control input setup time(slow) tis 0.7 0.8 ns 16~19 address and control input hold time(slow) tih 0.7 0.8 ns 16~19 data-out high impedence time from ck/ck thz -0.65 +0.65 -0.7 +0.7 ns 11 data-out low impedence time from ck/ck tlz -0.65 +0.65 -0.7 +0.7 ns 11 mode register set cycle time tmrd 10 12 ns dq & dm setup time to dqs tds 0.4 0.45 ns j, k dq & dm hold time to dqs tdh 0.4 0.45 ns j, k control & address input pulse width tipw 2.2 2.2 ns 18 dq & dm input pulse width tdipw 1.75 1.75 ns 18 exit self refresh to non-read command txsnr 75 75 ns exit self refresh to read command txsrd 200 200 tck refresh interval time trefi 7.8 7.8 us 14 output dqs valid window tqh thp -tqhs - thp -tqhs -ns21 clock half period thp tclmin or tchmin - tclmin or tchmin - ns 20, 21 data hold skew factor tqhs 0.5 0.55 ns 21 dqs write postamble time twpst 0.4 0.6 0.4 0.6 tck 12 active to read with auto precharge command trap 15 18 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 23 12.0 ac timming param eters & specifications www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 the following specification parame ters are required in systems us ing ddr333 devices to ensure pr oper system performance. these characteristics are for system simulation purposes and are guaranteed by design. table 1 : input slew rate fo r dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate table 4 : input/output setup & hold de rating for rise/fall delta slew rate table 5 : output slew rate char acteristice (x4, x8 devices only) table 6 : output slew rate characteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics ac characteristics ddr400 ddr333 parameter symbol min max min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew tbd tbd tbd tbd v/ns a, m input slew rate ? tis ? tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate ? tds ? tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k delta slew rate ? tds ? tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr400 ddr333 parameter min max min max notes output slew rate matching ratio (pullup to pulldown) tbd tbd tbd tbd e,m 13.0 system characteri stics for ddr sdram www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electr ical, ac and dc characterist ics, may be conducted at nominal reference/supply voltage l evels, but the related speci- fications and device operation are guaranteed for the full voltage range specified. 3. figure 1 represents the timing reference load used in defini ng the relevant timing parameters of the part. it is not int ended to be either a precise rep- resentation of the typical system environment nor a depiction of the actual load pr esented by a production tester. system desi gners will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers will correlate to their p roduction test conditions (generally a coaxial transmission line term inated at the tester electronics). 4. ac timing and idd tests may use a vil to vih swing of up to 1.5 v in the test environment, but input timing is still refere nced to vref (or to the cross- ing point for ck/ck), and parameter specifications are guaranteed fo r the specified ac input levels under normal use conditions . the minimum slew rate for the input signals is 1 v/ns in the range between vil(ac) and vih(ac). 5. the ac and dc input level specificati ons are as defined in the sstl_2 standard (i .e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input low (hig h) level. 6. inputs are not recognized as valid until vref stabiliz es. exception: during the peri od before vref stabilizes, cke 0.2vddq is recognized as low. 7. enables on.chip refresh and address counters. 8. idd specifications are tested af ter the device is properly initialized. 9. the ck/ck input reference level (for timing referenced to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck , is vref. 10. the output timing reference voltage level is vtt. 11. thz and tlz transitions occur in the same access time window s as valid data transitions. thes e parameters are not reference d to a specific voltage level but specify when the device output is no longer driving (hz), or begins driving (lz). 12. the maximum limit for this parameter is not a device limit. the device will operate with a gr eater value for this parameter , but sys tem performance (bus turnaround) will degrade accordingly. 13. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge . a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, dqs will be tran sitioning from high- z to logic low. if a previous write was in progress, dq s could be high, low, or transitioning fro m high to low at this time, depending on tdqss. 14. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 15. for command/address input slew rate 1.0 v/ns 16. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns 17. for ck & ck slew rate 1.0 v/ns 18. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by de vice design or tester correlation. 19. slew rate is measured between voh(ac) and vol(ac). 20. min (tcl, tch) refers to the smaller of the actual clock lo w time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch).....for example, tcl and tch ar e = 50% of the period, less the half per iod jitter (tjit(hp)) of the clock source, and less the half peri od jitter due to crosstalk (tjit(cro sstalk)) into the clock traces. 21. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defi ned by clock high or clock low (tch, tcl). tqhs accounts for 1) the pulse duration dis- tortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in o f dq on the next transi- tion, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers. 22. tdqsq - consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers fo r any given cycle. 23. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5ns tdal = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tdal = 5 clocks output vddq 50 ? 30pf (vout) figure 1 : timing reference load 14.0 component notes www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 b. pulldown slew rate is measured under the test conditions shown in figure 3. output test point vddq 50 ? figure 3 : pulldown sl ew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are sw itching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.5v(for ddr266/33 3) and 2.6v(for ddr400), typical process minimum : 70 c (t ambient), vddq = 2.3v(for ddr266/333) and 2.5v(for ddr400), slow - slow process maximum : 0 c (t ambient), vddq = 2.7v(for ddr266/333) and 2.7v(for ddr400), fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is s pecified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. verified under typical conditi ons for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5v/ns as shown in ta ble 2. the input slew rate is based on the lesser of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vi l(dc), similarly for rising trans itions. j. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc del ta rise, input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall ra te is calculated as: {1/(s lew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where the i/o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rates deter mined by eith er vih(ac) to vil(ac) or vih(dc) to vil(dc), and similarly for rising transitions. m. dqs, dm, and dq input slew rate is specified to prevent double clocking of dat a and preserve setup and hold times. signal tr ansi tions through the dc region must be monotonic. a. pullup slew rate is characteristized under the test conditions as shown in figure 2. output test point vssq 50 ? figure 2 : pullup slew rate test load 15.0 system notes: www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 (v=valid, x=don t care, h=logic high, l=logic low) note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be i ssued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be iss ued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the as sociated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and da ta-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any functi on, which means "no operation(nop)" in ddr sdram. command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9 a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address (a0~a9, a11,a12) read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down mode entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 16.0 command truth table www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 17.1 32m x 64 (m368l3324bt(u)) 17.0 physical dimensions tolerances : 0.005(.13) unless otherwise specified. the used device is 32mx16 ddr sdram, tsopii. ddr sdram part no : k4h511638b 5.25 0.005 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.100 (2.30) 0.393 (10.00) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b a b (128.950) (133.350 0.13 ) 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (64.77) (49.53) (17.80) 2.55 1.95 2.500 +0.1/-0.0 0.7 0.10 m c ba 0.10 m c a 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 1.25 0.006 (31.75 0.15) (4.00 0.1 ) (2x) 0.157 0.098 max 0.050 0.0039 (1.270 0.10) (2.47 max) m b (3.00 min) 0.118 min www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 17.2 64mx64 (m368l6523bt(u)) tolerances : 0.005(.13) unless otherwise specified. the used device is 64mx8 ddr sdram, tsopii. ddr sdram part no : k4h510838b 5.25 0.005 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.100 (2.30) 0.393 (10.00) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b a b (128.950) (133.350 0.13) 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (64.77) (49.53) (17.80) 2.55 1.95 2.500 +0.1/-0.0 0.7 0.10 m c ba 0.1496 (3.00min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 1.25 0.006 (31.75 0.15) (4.00 0.1 ) (2x) 0.157 0.10 m c a m b (3.00min) 0.118 min 0.07 max 0.050 0.0039 (1.270 0.10) (1.20 max) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 17.3 64mx72 (m381l6523bt(u)) tolerances : 0.005(.13) unless otherwise specified. the used device is 64mx8 ddr sdram, tsopii. ddr sdram part no : k4h510838b 5.25 0.005 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.100 (2.30) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.13) 0.250 (6.350) detail a 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (64.77) (49.53) (17.80) 2.55 1.95 2.500 +0.1/-0.0 0.7 0.10 m c ba 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 1.25 0.006 (31.75 0.15) (4.00 0.1 ) (2x) 0.157 0.10 m c a m b (3.00 min) 0.118 min 0.07 max 0.050 0.0039 (1.270 0.10) (1.20 max) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 17.4 128mx64 (m368l2923bt(u)) tolerances : 0.005(.13) unless otherwise specified. the used device is 64mx8 ddr sdram, tsopii. ddr sdram part no : k4h510838b 5.25 0.005 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.145 max 0.050 0.0039 (1.270 0.10) 0.100 (2.30) 0.393 (10.00) (1.270) 0.100 0.0079 (2.50 0.2 ) detail b a b (128.950) (133.350 0.13) 0.250 (6.350) detail a 0.071 (1.80) (3.67 max) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (64.77) (49.53) (17.80) 2.55 1.95 2.500 +0.1/-0.0 0.7 0.10 m c ba 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 1.25 0.006 (31.75 0.15) (4.00 0.1 ) (2x) 0.157 0.10 m c a m b (3.00 min) 0.118 min www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
ddr sdram 256mb, 512mb, 1gb unbuffered dimm rev. 1.1 june 2005 17.5 128mx72 (m381l2923bt(u)) tolerances : 0.005(.13) unless otherwise specified. the used device is 64mx8 ddr sdram, tsopii. ddr sdram part no : k4h510838b 5.25 0.005 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.145 max 0.050 0.0039 (1.270 0.10) 0.100 0.005 (2.30 0.13) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.13) 0.250 (6.350) detail a 0.071 (1.80) (3.67 max) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (64.77) (49.53) (17.80) 2.55 1.95 2.500 +0.1/-0.0 0.7 0.10 m c ba 0.1496 (3.00 min) 0.118 min r (2.00) 0.0787 (4.00 0.1 ) 0.1575 0.004 1.25 0.006 (31.75 0.15) (4.00 0.1 ) (2x) 0.157 0.10 m c a m b (3.00 min) 0.118 min www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet

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